*EL5163 Macromodel 每 also used for the following related devices *EL5162 (EL5162 with disable feature 每 disable feature is not modeled) *EL5262,EL5263 (dual channel versions) *EL5362 (triple channel version) * *Revision History: Rev. 3,Oct. 2009 by Jian Wang *Rev. 4, March 2010, Added/Correcting Input/Output headroom limits (by Jian Wang) *Intended use: This Pspice Macromodel is intended to give typical DC and AC *performance characteristics under a wide range of external circuit configurations *using compatible simulation platforms 每 such as iSim PE. * *Device performance features supported by this model: *Typical, room temp., nominal power supply voltages used to produce the following characteristics *Open and closed loop I/O impedances *Open loop gain and phase *Closed loop bandwidth and frequency response peaking under different external conditions *Loading effects on closed loop frequency response *Input noise terms including 1/f effects *Slew rate *Input and Output Headroom limits to I/O voltage swing *Supply current at nominal specified supply voltages *Nominal input DC error terms (1/3 of specified data sheet test or specified limits *每 intended to give 1考 error term on one polarity) *Load current reflected into the power supply current * *Device performance features NOT supported by this model: *Harmonic distortion effects *Composite video differential gain and phase errors *Output current limiting (if any) *Disable operation (if any) *Thermal effects and/or over temperature parameter variation *Limited performance variation vs. supply voltage is modeled *Part to part performance variation due to normal process parameter spread *Any performance difference arising from different packaging * *LICENSE STATEMENT *The information in this SPICE model is protected under *the United States copyright laws. Intersil Corporation hereby *grants users of this macro-model hereto referred to *as "Licensee", a nonexclusive, nontransferable license to use *this model as long as the Licensee abides by the terms of this agreement. *Before using this macro-model, the Licensee should read this license. *If this Licensee does not accept these terms, *permission to use the model is not granted. *The Licensee may not sell, loan, rent, or license the macro-model, *in whole, in part, or in modified form, to anyone *outside the Licensee's company. The Licensee may *modify the macro-model to suit his/her specific applications, *and the Licensee may make copies of this macro-model for use within *their company only. *This macro-model is provided "AS IS, WHERE IS, AND WITH NO *WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT *NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *FOR A PARTICULAR PURPOSE." *In no event will Intersil be liable for special, collateral, *incidental, or consequential damages in connection with or arising *out of the use of this macro-model. Intersil reserves the right to *make changes to the product and the macro-model without prior notice. * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt EL5163 3 2 7 4 6 * G_G7 7 6 7 VV5 -0.02 D_DN2 104 103 Iden D_D7 4 15 DY G_Gi2 5 9 5 9 0.001 C_C9 4 VV5 0.001p R_R22 0 103 140 R_R25 0 NI1 0.0051 C_C4 4 VV2 0.57p C_C10 VV5 7 0.001p G_G2 VV2 4 12 4 0.01 D_D6 7 17 DX G_G1 7 VV2 7 11 0.01 R_R17 13 0 1G V_V16 104 0 0.4Vdc D_D9 19 11 DX R_R13 6 7 50 C_C5 VV3 7 0.0085p D_D3 13 7 DX R_R23 0 NI2 0.012 C_Cin1 0 3 1.7p V_V15 102 0 0.4Vdc V_V7 7 19 1.5dc G_G9 7 VV4 VV3 16 0.00001 R_R14 4 6 50 G_Gb1 7 2 1 16 0.000001 D_D5 7 15 DX E_EN N4150175 3 101 103 1 Q_Q4 12 10 2 Ipnp G_G10 4 VV4 VV3 16 0.00001 I_I2 7 5 DC 50uAdc G_Gn1 3 0 NI1 0 1 I_I1 8 4 DC 50uAdc C_Cs1 2 7 0.25p R_R10 4 VV3 100k G_G4 7 VV3 VV2 16 0.00001 G_Gn2 2 0 NI2 0 1 E_E3 16 4 7 4 0.5 I_Ib1 7 1 DC 0.5uAdc C_C3 VV2 7 0.57p G_G11 7 VV5 VV4 16 0.00001 R_R11 VV4 7 100k C_C6 4 VV3 0.0085p G_G6 17 4 VV5 6 0.0001 R_R26 0 NI1 0.0051 I_Ib2 7 2 DC 2uAdc D_D4 4 14 DX V_Vos 1 N4150175 1.5mVdc C_Cs2 4 2 0.25p D_DN1 102 101 Iden V_V6 VV2 14 1.5Vdc G_G12 4 VV5 VV4 16 0.00001 R_R12 4 VV4 100k Q_Q3 4 1 5 Ipnp R_R24 0 NI2 0.012 G_Gi1 8 10 8 10 0.001 R_R18 14 0 1G G_G5 15 4 6 VV5 0.0001 D_D10 12 18 DX C_C2 4 10 0.002p R_R21 0 101 140 C_C7 4 VV4 0.001p D_D8 4 17 DY C_C1 9 7 0.002p G_Gi4 7 11 7 11 0.0125 G_Gi3 12 4 12 4 0.0125 V_V8 18 4 1.5Vdc R_R7 VV2 7 1G C_C8 VV4 7 0.001p Q_Q2 11 9 2 Inpn G_G8 6 4 VV5 4 -0.02 R_R15 VV5 7 100k V_V5 13 VV2 1.5Vdc R_R8 4 VV2 1G R_R9 VV3 7 100k G_G3 4 VV3 VV2 16 0.00001 Q_Q1 7 1 8 Inpn R_R16 4 VV5 100k * Models * .model Ipnp pnp(is=1e-15 bf=1E9 VAF=65) .model Inpn npn(is=1e-15 bf=1E9 VAF=65) .model Iden d(kf=100e-14 af=1) .MODEL DY D(IS=1E-20 BV=50 Rs=1) .MODEL DX D(IS=1E-15 Rs=1) .ends EL5163