*EL5166 Macromodel 每 also used for the following related devices *EL5167 (EL5166 with disable feature 每 disable feature is not modeled) * *Revision History: Rev. 3,Oct. 2009 by Jian Wang *Rev. 4, March 2010, Added/Correcting Input/Output headroom limits (by Jian Wang) *Intended use: This Pspice Macromodel is intended to give typical DC and AC *performance characteristics under a wide range of external circuit configurations *using compatible simulation platforms 每 such as iSim PE. * *Device performance features supported by this model: *Typical, room temp., nominal power supply voltages used to produce the following characteristics *Open and closed loop I/O impedances *Open loop gain and phase *Closed loop bandwidth and frequency response peaking under different external conditions *Loading effects on closed loop frequency response *Input noise terms including 1/f effects *Slew rate *Input and Output Headroom limits to I/O voltage swing *Supply current at nominal specified supply voltages *Nominal input DC error terms (1/3 of specified data sheet test or specified limits *每 intended to give 1考 error term on one polarity) *Load current reflected into the power supply current * *Device performance features NOT supported by this model: *Harmonic distortion effects *Composite video differential gain and phase errors *Output current limiting (if any) *Disable operation (if any) *Thermal effects and/or over temperature parameter variation *Limited performance variation vs. supply voltage is modeled *Part to part performance variation due to normal process parameter spread *Any performance difference arising from different packaging * *LICENSE STATEMENT *The information in this SPICE model is protected under *the United States copyright laws. Intersil Corporation hereby *grants users of this macro-model hereto referred to *as "Licensee", a nonexclusive, nontransferable license to use *this model as long as the Licensee abides by the terms of this agreement. *Before using this macro-model, the Licensee should read this license. *If this Licensee does not accept these terms, *permission to use the model is not granted. *The Licensee may not sell, loan, rent, or license the macro-model, *in whole, in part, or in modified form, to anyone *outside the Licensee's company. The Licensee may *modify the macro-model to suit his/her specific applications, *and the Licensee may make copies of this macro-model for use within *their company only. *This macro-model is provided "AS IS, WHERE IS, AND WITH NO *WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT *NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *FOR A PARTICULAR PURPOSE." *In no event will Intersil be liable for special, collateral, *incidental, or consequential damages in connection with or arising *out of the use of this macro-model. Intersil reserves the right to *make changes to the product and the macro-model without prior notice. * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt EL5166 Vin+ Vin- V+ V- Vout * G_G14 V+ VV4 VV3 10 0.00001 G_G11 V+ VOUT V+ VV5 -0.02 D_DN2 104 103 Iden D_D7 V- 13 DY G_G17 V- VV5 VV4 10 0.00001 R_R26 0 NI1 0.302 R_R22 0 103 2.5k C_Cin1 0 VIN+ 1.5p R_R11 VV4 V+ 100k R_R24 0 NI2 0.0437 R_R16 V- VV5 100k R_R17 11 0 1G R_R18 12 0 1G C_C4 V- VV2 0.282p G_G6 VV2 V- 7 V- 0.0125 C_C7 VV4 V+ 0.001p D_D6 V+ 14 DX R_R1014 14 0 1G C_C10 V- VV5 0.0005p G_G5 V+ VV2 V+ 6 0.0125 V_V16 104 0 1.5Vdc D_D9 N47157140 6 DX R_R13 VOUT V+ 50 C_C5 VV3 V+ 0.002p D_D3 11 V+ DX V_V15 102 0 1.5Vdc V_V7 V+ N47157140 0.1Vdc R_R1007 N47157140 0 1G R_R14 V- VOUT 50 G_G13 V+ VIN- 1 10 0.0000007 C_C2 4 V+ 0.06p D_D5 V+ 13 DX R_R1013 13 0 1G E_EN N4150175 VIN+ 101 103 1 Q_Q4 7 5 VIN- Ipnp I_I2 V+ 2 DC 150uAdc R_R25 0 NI1 0.302 G_G15 V- VV4 VV3 10 0.00001 I_I1 3 V- DC 150uAdc C_Cs1 VIN- V+ 0.2p R_R10 V- VV3 100k G_G4 V+ 6 V+ 6 0.0125 G_G7 V+ VV3 VV2 10 0.00001 G_G3 7 V- 7 V- 0.0125 E_E3 10 V- V+ V- 0.5 I_Ib1 V+ 1 DC 0.7uAdc G_G1 3 5 3 5 0.00015 C_C3 VV2 V+ 0.282p C_C6 V- VV3 0.002p R_R12 V- VV4 100k G_G10 14 V- VV5 VOUT 0.001 I_Ib2 V+ VIN- DC 8.5uAdc C_C1 V- 5 0.06p G_G16 V+ VV5 VV4 10 0.00001 D_D4 V- 12 DX G_G2 2 4 2 4 0.00015 V_Vos 1 N4150175 0.5mVdc C_Cs2 V- VIN- 0.2p D_DN1 102 101 Iden R_R23 0 NI2 0.0437 V_V6 VV2 12 1.3Vdc Q_Q2 V- 1 2 Ipnp C_C8 V- VV4 0.001p I_I3 V+ V- DC 7mAdc G_G9 13 V- VOUT VV5 0.001 R_R15 VV5 V+ 100k D_D10 7 N4721245 DX R_R21 0 101 2.5k D_D8 V- 14 DY G_Gn1 VIN+ 0 NI1 0 1 C_C9 VV5 V+ 0.0005p V_V8 N4721245 V- 0.1Vdc R_R1008 N4721245 0 1G R_R7 VV2 V+ 10meg Q_Q3 6 4 VIN- Inpn G_G12 VOUT V- VV5 V- -0.02 V_V5 11 VV2 1.3Vdc R_R8 V- VV2 10meg R_R9 VV3 V+ 100k G_G8 V- VV3 VV2 10 0.00001 G_Gn2 VIN- 0 NI2 0 1 Q_Q1 V+ 1 3 Inpn * * Models * .model Ipnp pnp(is=1e-15 bf=1E9 VAF=35) .model Inpn npn(is=1e-15 bf=1E9 VAF=35) .model Iden d(kf=1.6e-15 af=1) .MODEL DX D(IS=1E-15 Rs=1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends EL5166